Power Integrity Analysis

AEi Systems Offers Power Integrity Analysis as a service. Using your boards files, we analyze the design, creating all the necessary VRM, decoupling capacitors, bead, and PDN models. We generate the PDN impedance and Regulator Noise and assess system performance.

PDN Analysis - Benefits are HUGE

• Identify power distribution problems early


• Reduce prototype and production board spins


• Identify difficult-to-troubleshoot PCB problems


• Improve Memory, FPGA and High-Speed Circuitry Reliability

PDN Analysis - Why you need to perform this analysis

• Impedance profile impacts regulation margins - Must be flat!


• Decoupling is not intuitive - Value selection complex


• Need to take the PCB into account


• Capacitor and Via placement is critical


• The VRM impedance impacts the PDN - VRM, Plane, and IC all interact


• On-Die parasitics are not always known - Simulation allows exploration and bounding


• Need to understand crosstalk and plane noise propagation


• Rules of Thumb are insufficient


• Part Tolerances DRAMATICALLY Impact PDN Impedance Resonances


• Test is expensive and often impractical - Especially if there is no hardware

Power Integrity has become a huge concern for all designs. Power distribution network (PDN) design continues to be a major challenge in electronic systems. Integrated circuit performance is directly related to the quality of power distribution networks. Circuit timing and jitter characteristics are a strong functions of noise on the power supply. The quality of on-die power, jitter, and timing performance are highly dependent upon the PDN. Designing a clean and reliable power delivery network for a PCB design is a challenging but necessary exercise. It normally takes at least two (2) board spins to get right.

Figure 1. Components of a PDN system

The major components of the power delivery network are the die, package, the PCB planes, vias and traces, and the voltage regulator module. There are also several types of decoupling capacitors as well. The role of the decoupling capacitors is to help the voltage regulator supply current when there is high demand. Each of the system components contributes to the overall inductance of the PDN. Even the capacitors themselves have an inductance (ESL) that plays a role. The goal is to decouple this inductance to maintain the target impedance.

While Power Integrity analysis has been a very active field, in recent years it has started to attract more attention and it now shares the stage with Signal Integrity as one of the top concerns for high-speed digital designers. From the perspective of a high-speed digital designer, Power Integrity analysis involves looking at how the entire power delivery network responds when there is a change in current (di/dt) and how that affects the power rail that is connected to chips on the PCB. Since the entire PDN is inductive, when you have a large change in current, the power rail will droop due to L * di/dt. A droop (or bounce) in your power and ground rails can cause timing errors at your receiver inputs and add jitter to your sensitive interfaces. It is desirable to keep the power rail noise within a specified range to limit the impact on your system margins.





The major concern is the transient noise caused by the interaction of the PDN impedance with the dynamic currents of the FPGA, memory, and other high speed loads. As voltages levels are reduced and edge speeds increase, the window of acceptable voltage range narrows, reducing margins especially in the worst case. Computing just the DC component is not sufficient. The largest contributor is often the transient load step excursions. In the past, this was assessed by load stepping the regulator. This is no longer adequate given what we care about is the voltage at the load, not at the VRM output.